1. Field of the Invention
The present invention relates to a semiconductor device including a multi-finger type metal oxide semiconductor (MOS) transistor. In particular, the present invention relates to a semiconductor device using an n-type MOS (NMOS) transistor as an electrostatic discharge (hereinafter, referred to as ESD) protection element.
2. Description of the Related Art
In a semiconductor device including MOS transistors, an off transistor, which is an NMOS transistor provided in an off-state whose gate potential is fixed to a ground (Vss), is used as an ESD protection element for preventing breakdown of an internal circuit due to static electricity supplied from a pad provided for external connection.
Since the off transistor must flow a large amount of current generated by static electricity at once unlike ordinary MOS transistors forming an internal circuit such as a logic circuit, the off transistor is formed to have a large width (width W) of about several hundred micrometers in many cases.
Accordingly, the off transistor often takes a form of multi-finger which is obtained by combining a plurality of drain regions, source regions, and gate electrodes into a comb shape.
However, the combinatorial structure of a plurality of transistors causes a difficulty in uniformly operating the whole NMOS transistors for ESD protection. For example, current concentration occurs in a portion closer to the external connection terminal, resulting in the breakdown of the off transistor without sufficiently exhibiting the original ESD protection function.
As a countermeasure, there is proposed a method in which a distance between a contact hole formed on a drain region and a gate electrode is made smaller as a distance from the external connection terminal becomes longer to accelerate the operation of the transistor (for example, refer to FIG. 2 of JP 7-45829 A). There is also a proposal in which a length of a salicide block deposed on a drain region to protect the drain region from covering by the salicide is made longer as a distance from a substrate contact becomes longer to obtain a uniform operation of the transistor (for example, refer to JP 2007-116049 A).
When a width W is, for example, made smaller for a uniform operation of the off transistor, the protection function is, however, not sufficiently accomplished. Further, in the method of JP 7-45829 A, the distance between the contact and the gate electrode in the drain region is adjusted to thereby locally adjust a transistor operation speed. The method, however, has problems that a desired contact position cannot be ensured along with a reduction in width of the drain region, that line resistance has been made low through a use of an interconnect including a refractory metal in recent years to thereby accelerate the propagation speed of a surge, causing a case where the transistor operation speed cannot be adjusted only by the distance between the contact and the gate electrode, and that it is difficult to adapt the method to a case in which interconnect to the transistor is introduced from a direction perpendicular to the width direction of the transistor.
The patent document JP 2007-116049 A discloses a method for a local control of the operating speed of a transistor by adjusting the length of the salicide block on the drain region. The method, however, has problems that a predetermined length cannot be assured due to a variation caused in a manufacturing process, that line resistance has been made low through a use of an interconnect including a refractory metal in recent years to thereby accelerate the propagation speed of a surge, causing concentration of surges into a particular region of a salicide region, and that an occupation area by the NMOS off transistor increases due to an adjustment of the length of the salicide block.